1. Field of the Invention
The present invention relates to a phase-change memory device with overvoltage protection and to a method for protecting a phase-change memory device against over voltages.
2. Description of the Related Art
As is known, phase-change memory (PCM) elements exploit the characteristics of materials that have the property of changing between two phases having distinct electrical characteristics. For example, these materials may change from an amorphous phase, which is disorderly, to a crystalline or polycrystalline phase, which is orderly, and the two phases are associated to considerably different resistivity. Moreover, intermediate configurations, in which the material is only partially changed either to the amorphous or the crystalline phase, may be associated to intermediate resistivity values.
At present, alloys of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase-change cells. The chalcogenide that currently offers the most promise is formed by a Ge, Sb and Te alloy (Ge2Sb2Te5), which is currently widely used for storing information in overwritable disks. In chalcogenides, the resistivity varies by two or more magnitude orders when the material passes from the amorphous phase (more resistive) to the polycrystalline phase (more conductive) and vice versa.
The use of PCM elements for forming memory cells and arrays has already been proposed. In particular, in phase-change memories, a thin film of chalcogenic material is employed as a programmable resistor, which can be electrically heated by a controlled current so as to be switched between a high and a low resistance condition, and vice versa. The state of the chalcogenic material may be read by applying a small voltage and measuring the current passing through it. Since the current is proportional to the conductance of the chalcogenic material, it is possible to discriminate between the two states.
Regarding PCM reading, one of the problems to deal with is to prevent too high voltages from being accidentally applied either to selected or to unselected PCM cells of a memory array, even during transients. High voltages, in fact, may cause undesired phase transitions of some PCM cells and loss of information stored therein and, in any case, reading errors. In order to prevent high voltages and noise caused by adjacent memory cells, a respective selector, such as a PNP bipolar transistor, a MOS transistor or a diode, is generally associated to each PCM cell. The selectors are connected in series with the respective PCM cells: accordingly, a same current flows through a selected PCM cell and the corresponding selector, when the latter is turned on, whereas only negligible leakage currents may flow otherwise.
Anyway, the selectors may fail to protect the PCM cells. In fact, a selected PCM cell (or cells) is biased for reading through a respective bit line, which is maintained at a predetermined and constant bit line reading voltage. Since the selected PCM cell and the corresponding selector form a voltage divider which is fed with the bit line reading voltage, the voltage drop across the selected PCM cell is determined by the resistance ratio of the divider. However, both the resistance of the PCM cell and the conductivity of the selector in its on-state show unpredictable fluctuations, so that the voltage drop across the selected PCM cell may vary. For example, PCM cells may be programmed in an intermediate configuration with intermediate resistance, instead of being fully amorphous or fully crystalline. Furthermore, the conduction current-control voltage characteristics of the selectors depend on temperature; since these characteristics, especially for bipolar transistors and diodes, are non-linear, the resistance ratio of the divider is greatly affected, and the voltage drop across the selected PCM cell is consequently modified. FIG. 1 shows how the divider ratio may be influenced by the state of the PCM cell. In particular, the I–V characteristic of the selector is illustrated as a solid line, and the I–V characteristics of a PCM cell in a first and in a second state are shown as a dashed line and, respectively, as a dash-dot line (the first and the second state correspond to the same logic value, but the PCM cell resistivity is slightly higher in the second state than in the first state). In FIG. 1, VBL is the reading bit line voltage, VCELL1, VCELL2 are the voltage drops across the PCM cell in the first and, respectively, the second state, and VSEL1, VSEL2 are the control voltages of the selector in the two cases. In particular, the control voltage of the selector may fall to a very low value, so that the voltage drop across the selected PCM cell increases nearly up to the reading bit line voltage. Hence, in this case, the information stored in the PCM cell may be lost and reading errors may occur.